Nonvolatile memory cells with a magnetoresistive resistance, also called MRAM memory cells, usually have a layer sequence that includes a combination of ferromagnetic materials and an insulator layer respectively situated in between. The insulator layer is also referred to as a tunnel dielectric. In this case, the memory effect resides in the magnetically variable electrical resistance of the memory cell or memory cells.
The ferromagnetic materials have a magnetization axis per layer. The axes are arranged parallel to one another, thus resulting in two possible settings of the magnetization direction per layer. Depending on the magnetization state of the memory cell, the magnetization directions in the magnetic layers may be oriented in a parallel or antiparallel fashion. Depending on the relative orientation with respect to one another, the memory cell has a different electrical resistance. In this case, a parallel magnetization direction leads to a lower electrical resistance in the memory cell, while an antiparallel magnetization direction leads to a higher resistance.
The layers are generally embodied such that only one of the two ferromagnetic layers changes its magnetization state under the influence of an induced magnetic field, while the other layer has a time-invariant state, i.e., it serves as reference magnetization direction for the cell.
The insulator layer may have, for example, a thickness of about 1 to 3 nm. The electrical conductivity through this layer system is substantially determined by a tunnel effect through the insulator layer. Variations in the tunnel insulator thickness lead to great variations in the conductivity since the insulator thickness has an approximately exponential influence on the tunneling current.
The process of writing to such a memory cell is effected by an electric current. For this purpose, the memory cell is constructed such that it has two mutually crossing electrical conductors, called word line and bit line hereinafter. A layer sequence including magnetic layers and tunnel dielectric layers as described above is, in each case, provided at the crossover point between the conductors. An electric current flows through the two conductors, and in each case generates a magnetic field. The magnetic field resulting from a superposition of these fields acts on the individual magnetic layers. If the magnetic field strength is sufficiently large in each case, the magnetic layers exposed to the field are subject to magnetization reversal.
There are many possibilities that can be used as read-out methods for evaluating the memory cell content. For example, it is possible to perform a direct evaluation of the cell resistance and, if appropriate, a subsequent comparison with a reference resistance for instance of another cell. In this case, however, the problem arises that the abovementioned variations in the tunnel oxide thickness even of adjacent cells can lead to parameter fluctuations which can outweigh the difference to be measured in the magnetoresistive resistance in the order of magnitude of 10-20%.
As an alternative, it is also possible to employ directly switching reading. In this case, during the current measurement for determining the memory cell resistance, the latter is impressed with such a high value that a magnetization reversal, i.e., a reprogramming, of the cell content is performed. In this case, if the current intensity changes on account of an altered resistance in the case of a known magnetization state of the cell, then the state before the current was connected in is known. The same applies correspondingly to the case where no change is present. However, the high cell resistances in the case of a low voltage give rise in this case to the disadvantage that the expected change in the current lies in the thousandth range, and is thus difficult to detect. Primarily, however, this reading method is destructive, i.e., in the case of a change in resistance, it is necessary to re-establish the memory cell content before the reading operation.
A further possibility is described in DE 199 47 118 A1. Two voltages are successively stored in each case in a capacitance, the values of which depend on the resistances in the memory cell before and after a programming or switching attempt. The voltages may in each case be defined with dedicated additional resistances in order, e.g., to enable a comparison in a differential amplifier. It is only in the event of a successful programming attempt that different voltages stored in the capacitances are obtained. In principle, however, a disadvantage arises in this case, too, namely that the original memory content has to be written in again as a result of destructive reading methods, and that time and energy have to be expended as a result of the complicated re-reading-in process. Furthermore, this solution has the disadvantage that although currents through nonselected word and bit lines can lead to a reduction of parasitic effects, the cell array size is inevitably limited thereby.